[llvm] [LLVM][AArch64] Correctly lower funnel shifts by zero. (PR #140058)

[Jay Foad via llvm-commits]

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@@ -7266,12 +7266,18 @@ static SDValue LowerFunnelShift(SDValue Op, SelectionDAG &DAG) {
     MVT VT = Op.getSimpleValueType();
 
     if (Op.getOpcode() == ISD::FSHL) {
+      if (ShiftNo->isZero())
+        return Op.getOperand(0);
+
       unsigned int NewShiftNo =
           VT.getFixedSizeInBits() - ShiftNo->getZExtValue();
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jayfoad wrote:

> Or to ask another, there is no way to represent `fshl(a,b,multiple_of_src_bit_length)` using `fshr`?

Correct. TargetLowering already copes with this, see: https://github.com/llvm/llvm-project/blob/3667f29dfd1100a0eda7bfc4584ba2cfb6880b94/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp#L8074

https://github.com/llvm/llvm-project/pull/140058