[llvm] [LLVM][AArch64] Correctly lower funnel shifts by zero. (PR #140058)

[Paul Walker via llvm-commits]

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@@ -7266,12 +7266,18 @@ static SDValue LowerFunnelShift(SDValue Op, SelectionDAG &DAG) {
     MVT VT = Op.getSimpleValueType();
 
     if (Op.getOpcode() == ISD::FSHL) {
+      if (ShiftNo->isZero())
+        return Op.getOperand(0);
+
       unsigned int NewShiftNo =
           VT.getFixedSizeInBits() - ShiftNo->getZExtValue();
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paulwalker-arm wrote:

Sorry, I misinterpreted the ISD node description and thought out of range values were considered illegal.  I'll upload a fix, but the original issue still stands in that we must prevent `fshl(a,b,0)` from being rewritten as `fshr(a,b,0)`.

Or to ask another, there is no way to represent `fshl(a,b,multiple_of_src_bit_length)` using `fshr`?

https://github.com/llvm/llvm-project/pull/140058