[llvm] [AMDGPU] Implement hasAndNot for scalar bitwise AND-NOT operations. (PR #112647)

[Iris Shi via llvm-commits]

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@@ -17561,3 +17561,13 @@ SITargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
   AI->eraseFromParent();
   return LI;
 }
+
+bool SITargetLowering::hasAndNot(SDValue Op) const {
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el-ev wrote:

```suggestion
bool SITargetLowering::hasAndNot(SDValue Op) const {
  if (!Subtarget->isGCN())
    return false;
    
```

https://github.com/llvm/llvm-project/pull/112647