[llvm] [AMDGPU] Implement hasAndNot for scalar bitwise AND-NOT operations. (PR #112647)

[Iris Shi via llvm-commits]

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@@ -16890,3 +16889,13 @@ SITargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
   AI->eraseFromParent();
   return LI;
 }
+
+bool SITargetLowering::hasAndNot(SDValue Op) const {
+  // Return false if the operation is divergent, as AND-NOT is a scalar-only
+  // instruction.
+  if (Op->isDivergent() || !Op->isMachineOpcode())
+    return false;
+
+  EVT VT = Op.getValueType();
+  return VT == MVT::i32 || VT == MVT::i64;
+}
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el-ev wrote:

I searched the ISA documentations a few days ago and found that only AMDGCN subtargets have AndNot (S_ANDN2_{B32,B64}).

https://www.amd.com/content/dam/amd/en/documents/radeon-tech-docs/instruction-set-architectures/southern-islands-instruction-set-architecture.pdf
https://www.x.org/docs/AMD/old/r600isa.pdf

https://github.com/llvm/llvm-project/pull/112647