[llvm] [RISCV][Scheduler] Add scheduling definitions for 128-bit Zfa instructions (PR #140003)

[Iris Shi via llvm-commits]

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@@ -447,13 +450,16 @@ let Unsupported = true in {
 def : WriteRes<WriteFRoundF16, []>;
 def : WriteRes<WriteFRoundF32, []>;
 def : WriteRes<WriteFRoundF64, []>;
+def : WriteRes<WriteFRoundF128, []>;
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el-ev wrote:

I also found this piece of code wired, but prior to this change, it seems that an F+Zfa machine also defines WriteFRoundF64 although it doesn't support D.

https://github.com/llvm/llvm-project/pull/140003