[llvm] [RISCV][Scheduler] Add scheduling definitions for 128-bit Zfa instructions (PR #140003)

[Iris Shi via llvm-commits]

================
@@ -177,17 +177,24 @@ def FLEQ_H : FPCmp_rr<0b1010010, 0b100, "fleq.h", FPR16>;
 
 let Predicates = [HasStdExtZfa, HasStdExtQ] in {
 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
-def FLI_Q : FPFLI_r<0b1111011, 0b00001, 0b000, FPR128, "fli.q">;
+def FLI_Q : FPFLI_r<0b1111011, 0b00001, 0b000, FPR128, "fli.q">,
+            Sched<[WriteFLI128]>;
 
+let SchedRW = [WriteFMinMax128, ReadFMinMax128, ReadFMinMax128] in {
 def FMINM_Q: FPALU_rr<0b0010111, 0b010, "fminm.q", FPR128, Commutable=1>;
 def FMAXM_Q: FPALU_rr<0b0010111, 0b011, "fmaxm.q", FPR128, Commutable=1>;
+}
 
-def FROUND_Q : FPUnaryOp_r_frm<0b0100011, 0b00100, FPR128, FPR128, "fround.q">;
+def FROUND_Q : FPUnaryOp_r_frm<0b0100011, 0b00100, FPR128, FPR128, "fround.q">,
+               Sched<[WriteFRoundF128, ReadFRoundF128]>;
 def FROUNDNX_Q : FPUnaryOp_r_frm<0b0100011, 0b00101, FPR128, FPR128, 
-                                 "froundnx.q">;
+                                 "froundnx.q">,
+                 Sched<[WriteFRoundF128, ReadFRoundF128]>;
 
+let SchedRW = [WriteFCmp128, ReadFCmp128, ReadFCmp128] in {
----------------
el-ev wrote:

```
class Sched<list<SchedReadWrite> schedrw> {
  list<SchedReadWrite> SchedRW = schedrw;
}
```

There's actually no difference.

https://github.com/llvm/llvm-project/pull/140003