[llvm] langref updates for aarch64 trampoline (PR #139740)

[Jameson Nash via llvm-commits]

https://github.com/vtjnash updated https://github.com/llvm/llvm-project/pull/139740

>From 024576f47cef1c12a7181efb2dace9a4f885dc54 Mon Sep 17 00:00:00 2001
From: Jameson Nash <vtjnash at gmail.com>
Date: Tue, 13 May 2025 14:34:06 +0000
Subject: [PATCH 1/3] langref updates for aarch64 trampoline

Add clarifying comments to the langref from the review of #126743 (split
from the functional changes, to follow).
---
 llvm/docs/LangRef.rst | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index 5f14726c36672..da1824ba45175 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -410,8 +410,9 @@ added in the future:
       calling convention: on most platforms, they are not preserved and need to
       be saved by the caller, but on Windows, xmm6-xmm15 are preserved.
 
-    - On AArch64 the callee preserve all general purpose registers, except X0-X8
-      and X16-X18.
+    - On AArch64 the callee preserve all general purpose registers, except
+      X0-X8 and X16-X18. Using this calling convention with nest is forbidden
+      and may crash llvm.
 
     The idea behind this convention is to support calls to runtime functions
     that have a hot path and a cold path. The hot path is usually a small piece
@@ -447,9 +448,10 @@ added in the future:
       R11. R11 can be used as a scratch register. Furthermore it also preserves
       all floating-point registers (XMMs/YMMs).
 
-    - On AArch64 the callee preserve all general purpose registers, except X0-X8
-      and X16-X18. Furthermore it also preserves lower 128 bits of V8-V31 SIMD -
-      floating point registers.
+    - On AArch64 the callee preserve all general purpose registers, except
+      X0-X8 and X16-X18. Furthermore it also preserves lower 128 bits of V8-V31
+      SIMD floating point registers. Using this calling convention with nest is
+      forbidden and may crash llvm.
 
     The idea behind this convention is to support calls to runtime functions
     that don't need to call out to any other functions.
@@ -21120,7 +21122,12 @@ sufficiently aligned block of memory; this memory is written to by the
 intrinsic. Note that the size and the alignment are target-specific -
 LLVM currently provides no portable way of determining them, so a
 front-end that generates this intrinsic needs to have some
-target-specific knowledge. The ``func`` argument must hold a function.
+target-specific knowledge.
+
+The ``func`` argument must be a constant (potentially bitcasted) pointer to a
+function declaration or definition, since the calling convention may affect the
+content of the trampoline that is created.
+
 
 Semantics:
 """"""""""

>From 34d45bccb4aa66b79c9647932ee96160aa26905d Mon Sep 17 00:00:00 2001
From: Jameson Nash <vtjnash at gmail.com>
Date: Wed, 14 May 2025 11:46:23 -0400
Subject: [PATCH 2/3] Update LangRef.rst

---
 llvm/docs/LangRef.rst | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index da1824ba45175..593727a4dd1f1 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -411,8 +411,7 @@ added in the future:
       be saved by the caller, but on Windows, xmm6-xmm15 are preserved.
 
     - On AArch64 the callee preserve all general purpose registers, except
-      X0-X8 and X16-X18. Using this calling convention with nest is forbidden
-      and may crash llvm.
+      X0-X8 and X16-X18. Not allowed with nest.
 
     The idea behind this convention is to support calls to runtime functions
     that have a hot path and a cold path. The hot path is usually a small piece
@@ -450,8 +449,7 @@ added in the future:
 
     - On AArch64 the callee preserve all general purpose registers, except
       X0-X8 and X16-X18. Furthermore it also preserves lower 128 bits of V8-V31
-      SIMD floating point registers. Using this calling convention with nest is
-      forbidden and may crash llvm.
+      SIMD floating point registers. Not allowed with nest.
 
     The idea behind this convention is to support calls to runtime functions
     that don't need to call out to any other functions.

>From 04193da80a04d431c6189c04b0b779ccecb89e80 Mon Sep 17 00:00:00 2001
From: Jameson Nash <vtjnash at gmail.com>
Date: Wed, 14 May 2025 17:22:44 -0400
Subject: [PATCH 3/3] Update LangRef.rst

---
 llvm/docs/LangRef.rst | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index 593727a4dd1f1..fe985b118fc0a 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -411,7 +411,7 @@ added in the future:
       be saved by the caller, but on Windows, xmm6-xmm15 are preserved.
 
     - On AArch64 the callee preserve all general purpose registers, except
-      X0-X8 and X16-X18. Not allowed with nest.
+      X0-X8 and X16-X18. Not allowed with ``nest``.
 
     The idea behind this convention is to support calls to runtime functions
     that have a hot path and a cold path. The hot path is usually a small piece
@@ -449,7 +449,7 @@ added in the future:
 
     - On AArch64 the callee preserve all general purpose registers, except
       X0-X8 and X16-X18. Furthermore it also preserves lower 128 bits of V8-V31
-      SIMD floating point registers. Not allowed with nest.
+      SIMD floating point registers. Not allowed with ``nest``.
 
     The idea behind this convention is to support calls to runtime functions
     that don't need to call out to any other functions.