[llvm] langref updates for aarch64 trampoline (PR #139740)

[Eli Friedman via llvm-commits]

================
@@ -447,9 +447,9 @@ added in the future:
       R11. R11 can be used as a scratch register. Furthermore it also preserves
       all floating-point registers (XMMs/YMMs).
 
-    - On AArch64 the callee preserve all general purpose registers, except X0-X8
-      and X16-X18. Furthermore it also preserves lower 128 bits of V8-V31 SIMD -
-      floating point registers.
+    - On AArch64 the callee preserve all general purpose registers, except
+      X0-X8 and X16-X18. Furthermore it also preserves lower 128 bits of V8-V31
+      SIMD floating point registers. Not allowed with nest.
----------------
efriedma-quic wrote:

```suggestion
      SIMD floating point registers. Not allowed with ``nest``.
```

https://github.com/llvm/llvm-project/pull/139740