[llvm] [LLVM][TableGen] Code cleanup in FastISelEmitter.cpp (PR #139644)

[Rahul Joshi via llvm-commits]

================
@@ -304,77 +295,74 @@ struct OperandsSignature {
 
   void PrintParameters(raw_ostream &OS) const {
     ListSeparator LS;
-    for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
+    for (const auto [Idx, Opnd] : enumerate(Operands)) {
       OS << LS;
-      if (Operands[i].isReg()) {
-        OS << "Register Op" << i;
-      } else if (Operands[i].isImm()) {
-        OS << "uint64_t imm" << i;
-      } else if (Operands[i].isFP()) {
-        OS << "const ConstantFP *f" << i;
-      } else {
+      if (Opnd.isReg())
+        OS << "Register Op" << Idx;
+      else if (Opnd.isImm())
+        OS << "uint64_t imm" << Idx;
+      else if (Opnd.isFP())
+        OS << "const ConstantFP *f" << Idx;
+      else
         llvm_unreachable("Unknown operand kind!");
-      }
     }
   }
 
-  void PrintArguments(raw_ostream &OS,
-                      const std::vector<std::string> &PR) const {
-    assert(PR.size() == Operands.size());
+  void PrintArguments(raw_ostream &OS, ArrayRef<std::string> PhyRegs) const {
     ListSeparator LS;
-    for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
-      if (PR[i] != "")
+    for (const auto [Idx, Opnd, PhyReg] : enumerate(Operands, PhyRegs)) {
+      if (PhyReg != "") {
         // Implicit physical register operand.
         continue;
+      }
 
       OS << LS;
-      if (Operands[i].isReg()) {
-        OS << "Op" << i;
-      } else if (Operands[i].isImm()) {
-        OS << "imm" << i;
-      } else if (Operands[i].isFP()) {
-        OS << "f" << i;
-      } else {
+      if (Opnd.isReg())
+        OS << "Op" << Idx;
+      else if (Opnd.isImm())
+        OS << "imm" << Idx;
+      else if (Opnd.isFP())
+        OS << "f" << Idx;
+      else
         llvm_unreachable("Unknown operand kind!");
-      }
     }
   }
 
   void PrintArguments(raw_ostream &OS) const {
     ListSeparator LS;
-    for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
+    for (const auto [Idx, Opnd] : enumerate(Operands)) {
       OS << LS;
-      if (Operands[i].isReg()) {
-        OS << "Op" << i;
-      } else if (Operands[i].isImm()) {
-        OS << "imm" << i;
-      } else if (Operands[i].isFP()) {
-        OS << "f" << i;
-      } else {
+      if (Opnd.isReg())
+        OS << "Op" << Idx;
+      else if (Opnd.isImm())
+        OS << "imm" << Idx;
+      else if (Opnd.isFP())
+        OS << "f" << Idx;
+      else
         llvm_unreachable("Unknown operand kind!");
-      }
     }
   }
 
-  void PrintManglingSuffix(raw_ostream &OS, const std::vector<std::string> &PR,
+  void PrintManglingSuffix(raw_ostream &OS, ArrayRef<std::string> PhyRegs,
                            ImmPredicateSet &ImmPredicates,
                            bool StripImmCodes = false) const {
-    for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
-      if (PR[i] != "")
+    for (const auto [PR, Opnd] : zip_equal(PhyRegs, Operands)) {
+      if (PR != "") {
         // Implicit physical register operand. e.g. Instruction::Mul expect to
         // select to a binary op. On x86, mul may take a single operand with
         // the other operand being implicit. We must emit something that looks
         // like a binary instruction except for the very inner fastEmitInst_*
         // call.
         continue;
-      Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes);
+      }
+      Opnd.printManglingSuffix(OS, ImmPredicates, StripImmCodes);
     }
   }
 
   void PrintManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates,
                            bool StripImmCodes = false) const {
-    for (unsigned i = 0, e = Operands.size(); i != e; ++i)
-      Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes);
+    for (const OpKind Opnd : Operands)
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jurahul wrote:

Done

https://github.com/llvm/llvm-project/pull/139644