[llvm] [AArch64][SME] Disable hazard padding when there is only PPRs and GPRs (PR #137817)

[Benjamin Maxwell via llvm-commits]

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@@ -3533,6 +3533,12 @@ static std::optional<int> getLdStFrameID(const MachineInstr &MI,
   return getMMOFrameID(*MI.memoperands_begin(), MFI);
 }
 
+/// Returns true if PPRs are spilled as ZPRs.
+static bool arePPRsSpilledAsZPR(const MachineFunction &MF) {
+  return MF.getSubtarget().getRegisterInfo()->getSpillSize(
+             AArch64::PPRRegClass) == 16;
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MacDue wrote:

The usual case (via e.g. `str p4, [sp, ...]`). They're only spilled using Z registers when using the `aarch64-enable-zpr-predicate-spills` option (which expands the predicates to full vectors before storing them). 

https://github.com/llvm/llvm-project/pull/137817