[llvm] [AMDGPU] Eliminate unnecessary packing in wider f16 vectors for sdwa/opsel-able instruction (PR #137137)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,380 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -mcpu=gfx942 -run-pass si-peephole-sdwa,dead-mi-elimination -o - %s | FileCheck -check-prefixes=GFX9 %s
+
+--- |
+  source_filename = "/home/vikashgu/work/upstream/llvm-project/llvm/test/CodeGen/AMDGPU/vector-fp16.ll"
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arsenm wrote:

Don't need IR section 

https://github.com/llvm/llvm-project/pull/137137