[llvm] [AMDGPU] Implement hasAndNot for scalar bitwise AND-NOT operations. (PR #112647)

Matt Arsenault via llvm-commits llvm-commits at lists.llvm.org
Tue May 13 00:58:47 PDT 2025


================
@@ -16890,3 +16890,11 @@ SITargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
   AI->eraseFromParent();
   return LI;
 }
+
+bool SITargetLowering::hasAndNot(SDValue Op) const {
+  if (Op->isDivergent())
+    return false;
+
----------------
arsenm wrote:

Shouldn't really need to consider the machine opcode case 

https://github.com/llvm/llvm-project/pull/112647


More information about the llvm-commits mailing list