[llvm] [RISCV] Remove`riscv.segN.load/store` in favor of their mask variants (PR #137045)

[Harald van Dijk via llvm-commits]

hvdijk wrote:

Sorry, I should have been clearer. OpenCL device code can run on any device, it can run on CPU. We're translating OpenCL device code to run on CPUs, including RISC-V CPUs. You're right that the host code would not normally be expected to use address spaces, it's the device code using them.

https://github.com/llvm/llvm-project/pull/137045