[llvm] [NVPTX] Vectorize and lower 256-bit global loads/stores for sm_100+/ptx88+ (PR #139292)

[Drew Kersnar via llvm-commits]

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@@ -1483,44 +1495,27 @@ bool NVPTXDAGToDAGISel::tryStoreVector(SDNode *N) {
   const unsigned TotalWidth = StoreVT.getSimpleVT().getSizeInBits();
   unsigned ToType = getLdStRegType(StoreVT.getSimpleVT().getScalarType());
 
-  SmallVector<SDValue, 12> Ops;
-  SDValue N2;
-  unsigned VecType;
-  unsigned ToTypeWidth;
-
-  switch (N->getOpcode()) {
-  case NVPTXISD::StoreV2:
-    VecType = NVPTX::PTXLdStInstCode::V2;
-    Ops.append({N->getOperand(1), N->getOperand(2)});
-    N2 = N->getOperand(3);
-    ToTypeWidth = TotalWidth / 2;
-    break;
-  case NVPTXISD::StoreV4:
-    VecType = NVPTX::PTXLdStInstCode::V4;
-    Ops.append({N->getOperand(1), N->getOperand(2), N->getOperand(3),
-                N->getOperand(4)});
-    N2 = N->getOperand(5);
-    ToTypeWidth = TotalWidth / 4;
-    break;
-  default:
-    return false;
-  }
+  unsigned NumElts = getLoadStoreVectorNumElts(N);
+  SmallVector<SDValue, 16> Ops;
+  for (unsigned I : llvm::seq(NumElts))
+    Ops.append({N->getOperand(I + 1)});
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dakersnar wrote:

I think `Ops.append(N->ops().begin() + 1, N->ops().begin() + NumElts + 1);` would work, did you have something else in mind or does that look good to you?

https://github.com/llvm/llvm-project/pull/139292