[llvm] [NVPTX] Vectorize and lower 256-bit global loads/stores for sm_100+/ptx88+ (PR #139292)

[Alex MacLean via llvm-commits]

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@@ -2438,17 +2438,27 @@ multiclass LD_VEC<NVPTXRegClass regclass> {
          LdStCode:$Sign, i32imm:$fromWidth, ADDR:$addr),
     "ld${sem:sem}${scope:scope}${addsp:addsp}${Vec:vec}.${Sign:sign}$fromWidth "
     "\t{{$dst1, $dst2, $dst3, $dst4}}, [$addr];", []>;
+  if support_v8 then {
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AlexMaclean wrote:

nit: I would remove the curly braces here, and elsewhere when you only have a single element in the `if`.

https://github.com/llvm/llvm-project/pull/139292