[llvm] [TableGen] Fix computeRegUnitLaneMasks for ad hoc aliasing (PR #79835)

[Jay Foad via llvm-commits]

jayfoad wrote:

> don't you think each regunit corresponds to a distinct laneBitmask in a register. Now, in case of ad-hoc aliases, a shared(fake) regunit is created for both the leaf register (as in case of sx0 , sw0 & sf0). Now, if we have unique leaf regunit for each of these 2 leaf regs( as suggested by you [#79831 (comment)](https://github.com/llvm/llvm-project/pull/79831#issuecomment-1943746260):), then how RA will understand that both sw0 & sf0 are same (as regunits are used for interference check) thus losing the very reason of why ad-hoc-alias is used in first place

My suggestion is that SW0 and SF0 should each get a regunit that uniquely identifies them _as well as_ a shared regunit that represents the aliasing. For example:

SW0 regunits: 0, 1 // regunit 0 is for the aliasing
SF0 regunits: 0, 2 // regunit 0 is for the aliasing
SX0 regunits: 0, 1, 2 // inherits regunits from both its subregs

https://github.com/llvm/llvm-project/pull/79835