[llvm] [TableGen] Fix computeRegUnitLaneMasks for ad hoc aliasing (PR #79835)

[Vikash Gupta via llvm-commits]

vg0204 wrote:

>SW0 regunits: 0, 1 // regunit 0 is for the aliasing
>SF0 regunits: 0, 2 // regunit 0 is for the aliasing
>SX0 regunits: 0, 1, 2 // inherits regunits from both its subregs

Just a thought, even after that we would have invalid lanemask(0x0) for regUnit0, but for remaining regUnit1 & regUnit2, they will rightfully show the lanemask as calculated as per SubRegIdx in SX0 ! But, that's fine I guess right.



https://github.com/llvm/llvm-project/pull/79835