[llvm] [TableGen] Fix computeRegUnitLaneMasks for ad hoc aliasing (PR #79835)

[Vikash Gupta via llvm-commits]

vg0204 wrote:

@jayfoad , don't you think each regunit corresponds to a distinct laneBitmask in a register. Now, in case of ad-hoc aliases, a shared(fake) regunit is created for both the leaf register (as in case of sx0 , sw0 & sf0). Now, if we have unique leaf regunit for each of these 2 leaf regs( as suggested by you https://github.com/llvm/llvm-project/pull/79831#issuecomment-1943746260:), then how RA will understand that both sw0 & sf0 are same (as regunits are used for interference check) thus losing the very reason of why ad-hoc-alias is used in first place

https://github.com/llvm/llvm-project/pull/79835