[llvm] [RISCV] TableGen-erate RISC-V SDNodes (PR #138381)

[Sergei Barannikov via llvm-commits]

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@@ -17,6 +17,32 @@
 ///
 //===----------------------------------------------------------------------===//
 
+// Splats an 64-bit value that has been split into two i32 parts. This is
+// expanded late to two scalar stores and a stride 0 vector load.
+// The first operand is passthru operand.
+//
+// This is only present to generate the correct TableGen SDNode description,
+// it is lowered before instruction selection.
+// FIXME: I'm not sure the types here are entirely correct.
+// Returns a vector. Operand 0 is a passthru, operand 1 and 2 are i32 scalars, operand 3 is VL
+def riscv_splat_vector_split_i64_vl : RVSDNode<"SPLAT_VECTOR_SPLIT_I64_VL", 
+                                               SDTypeProfile<1, 4, [SDTCisVec<0>,
+                                                                    SDTCVecEltisVT<0, i64>, 
+                                                                    SDTCisSameAs<1, 0>,
+                                                                    SDTCisVT<2, i32>,
+                                                                    SDTCisVT<3, i32>,
+                                                                    SDTCisVT<4, XLenVT>]>>;
+
+def riscv_tuple_insert : RVSDNode<"TUPLE_INSERT",
+                                  SDTypeProfile<1, 3, [SDTCisSameAs<1, 0>,
+                                                       SDTCisVec<2>,
+                                                       SDTCisVT<3, i32>]>>;
+
+def riscv_tuple_extract : RVSDNode<"TUPLE_EXTRACT",
+                                  SDTypeProfile<1, 2, [SDTCisVec<0>,
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s-barannikov wrote:

Misindented by 1

https://github.com/llvm/llvm-project/pull/138381