[llvm] [RISCV] TableGen-erate RISC-V SDNodes (PR #138381)
Sergei Barannikov via llvm-commits
llvm-commits at lists.llvm.org
Sat May 3 02:41:56 PDT 2025
================
@@ -306,99 +368,117 @@ def any_riscv_uint_to_fp_vl : PatFrags<(ops node:$src, node:$mask, node:$vl),
[(riscv_uint_to_fp_vl node:$src, node:$mask, node:$vl),
(riscv_strict_uint_to_fp_vl node:$src, node:$mask, node:$vl)]>;
-def riscv_vfround_noexcept_vl: SDNode<"RISCVISD::VFROUND_NOEXCEPT_VL", SDT_RISCVFPUnOp_VL>;
-def riscv_strict_vfround_noexcept_vl: SDNode<"RISCVISD::STRICT_VFROUND_NOEXCEPT_VL", SDT_RISCVFPUnOp_VL, [SDNPHasChain]>;
+let HasMaskOp = true in {
+ def riscv_vfround_noexcept_vl: RVSDNode<"VFROUND_NOEXCEPT_VL", SDT_RISCVFPUnOp_VL>;
+
+ let IsStrictFP = true in
+ def riscv_strict_vfround_noexcept_vl: RVSDNode<"STRICT_VFROUND_NOEXCEPT_VL", SDT_RISCVFPUnOp_VL, [SDNPHasChain]>;
+}
def any_riscv_vfround_noexcept_vl : PatFrags<(ops node:$src, node:$mask, node:$vl),
[(riscv_vfround_noexcept_vl node:$src, node:$mask, node:$vl),
(riscv_strict_vfround_noexcept_vl node:$src, node:$mask, node:$vl)]>;
-def riscv_setcc_vl : SDNode<"RISCVISD::SETCC_VL", SDT_RISCVSETCCOP_VL>;
-def riscv_strict_fsetcc_vl : SDNode<"RISCVISD::STRICT_FSETCC_VL", SDT_RISCVSETCCOP_VL, [SDNPHasChain]>;
-def riscv_strict_fsetccs_vl : SDNode<"RISCVISD::STRICT_FSETCCS_VL", SDT_RISCVSETCCOP_VL, [SDNPHasChain]>;
+let HasPassthruOp = true, HasMaskOp = true in
+def riscv_setcc_vl : RVSDNode<"SETCC_VL", SDT_RISCVSETCCOP_VL>;
+
+let IsStrictFP = true, HasMaskOp = true in {
+ def riscv_strict_fsetcc_vl : RVSDNode<"STRICT_FSETCC_VL", SDT_RISCVSETCCOP_VL, [SDNPHasChain]>;
+ def riscv_strict_fsetccs_vl : RVSDNode<"STRICT_FSETCCS_VL", SDT_RISCVSETCCOP_VL, [SDNPHasChain]>;
+} // let IsStrictFP = true, HasMaskOp = true
+
def any_riscv_fsetcc_vl : PatFrags<(ops node:$lhs, node:$rhs, node:$cc, node:$passthru, node:$mask, node:$vl),
[(riscv_setcc_vl node:$lhs, node:$rhs, node:$cc, node:$passthru, node:$mask, node:$vl),
(riscv_strict_fsetcc_vl node:$lhs, node:$rhs, node:$cc, node:$passthru, node:$mask, node:$vl)]>;
def any_riscv_fsetccs_vl : PatFrags<(ops node:$lhs, node:$rhs, node:$cc, node:$passthru, node:$mask, node:$vl),
[(riscv_setcc_vl node:$lhs, node:$rhs, node:$cc, node:$passthru, node:$mask, node:$vl),
(riscv_strict_fsetccs_vl node:$lhs, node:$rhs, node:$cc, node:$passthru, node:$mask, node:$vl)]>;
-def riscv_vrgather_vx_vl : SDNode<"RISCVISD::VRGATHER_VX_VL",
- SDTypeProfile<1, 5, [SDTCisVec<0>,
- SDTCisSameAs<0, 1>,
- SDTCisVT<2, XLenVT>,
- SDTCisSameAs<0, 3>,
- SDTCVecEltisVT<4, i1>,
- SDTCisSameNumEltsAs<0, 4>,
- SDTCisVT<5, XLenVT>]>>;
-def riscv_vrgather_vv_vl : SDNode<"RISCVISD::VRGATHER_VV_VL",
- SDTypeProfile<1, 5, [SDTCisVec<0>,
- SDTCisSameAs<0, 1>,
- SDTCisInt<2>,
- SDTCisSameNumEltsAs<0, 2>,
- SDTCisSameSizeAs<0, 2>,
- SDTCisSameAs<0, 3>,
- SDTCVecEltisVT<4, i1>,
- SDTCisSameNumEltsAs<0, 4>,
- SDTCisVT<5, XLenVT>]>>;
-def riscv_vrgatherei16_vv_vl : SDNode<"RISCVISD::VRGATHEREI16_VV_VL",
+let HasMaskOp = true in {
+ def riscv_vrgather_vx_vl : RVSDNode<"VRGATHER_VX_VL",
+ SDTypeProfile<1, 5, [SDTCisVec<0>,
+ SDTCisSameAs<0, 1>,
+ SDTCisVT<2, XLenVT>,
+ SDTCisSameAs<0, 3>,
+ SDTCVecEltisVT<4, i1>,
+ SDTCisSameNumEltsAs<0, 4>,
+ SDTCisVT<5, XLenVT>]>>;
+ def riscv_vrgather_vv_vl : RVSDNode<"VRGATHER_VV_VL",
SDTypeProfile<1, 5, [SDTCisVec<0>,
- SDTCisSameAs<0, 1>,
- SDTCisInt<2>,
- SDTCVecEltisVT<2, i16>,
- SDTCisSameNumEltsAs<0, 2>,
- SDTCisSameAs<0, 3>,
- SDTCVecEltisVT<4, i1>,
- SDTCisSameNumEltsAs<0, 4>,
- SDTCisVT<5, XLenVT>]>>;
+ SDTCisSameAs<0, 1>,
+ SDTCisInt<2>,
+ SDTCisSameNumEltsAs<0, 2>,
+ SDTCisSameSizeAs<0, 2>,
+ SDTCisSameAs<0, 3>,
+ SDTCVecEltisVT<4, i1>,
+ SDTCisSameNumEltsAs<0, 4>,
+ SDTCisVT<5, XLenVT>]>>;
+ def riscv_vrgatherei16_vv_vl : RVSDNode<"VRGATHEREI16_VV_VL",
+ SDTypeProfile<1, 5, [SDTCisVec<0>,
+ SDTCisSameAs<0, 1>,
+ SDTCisInt<2>,
+ SDTCVecEltisVT<2, i16>,
+ SDTCisSameNumEltsAs<0, 2>,
+ SDTCisSameAs<0, 3>,
+ SDTCVecEltisVT<4, i1>,
+ SDTCisSameNumEltsAs<0, 4>,
+ SDTCisVT<5, XLenVT>]>>;
+} // let HasMaskOp = true
def SDT_RISCVVMERGE_VL : SDTypeProfile<1, 5, [
SDTCisVec<0>, SDTCisVec<1>, SDTCisSameNumEltsAs<0, 1>, SDTCVecEltisVT<1, i1>,
SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>, SDTCisSameAs<0, 4>,
SDTCisVT<5, XLenVT>
]>;
-def riscv_vmerge_vl : SDNode<"RISCVISD::VMERGE_VL", SDT_RISCVVMERGE_VL>;
+let HasPassthruOp = true in
+def riscv_vmerge_vl : RVSDNode<"VMERGE_VL", SDT_RISCVVMERGE_VL>;
def SDT_RISCVVMSETCLR_VL : SDTypeProfile<1, 1, [SDTCVecEltisVT<0, i1>,
SDTCisVT<1, XLenVT>]>;
-def riscv_vmclr_vl : SDNode<"RISCVISD::VMCLR_VL", SDT_RISCVVMSETCLR_VL>;
-def riscv_vmset_vl : SDNode<"RISCVISD::VMSET_VL", SDT_RISCVVMSETCLR_VL>;
+def riscv_vmclr_vl : RVSDNode<"VMCLR_VL", SDT_RISCVVMSETCLR_VL>;
+def riscv_vmset_vl : RVSDNode<"VMSET_VL", SDT_RISCVVMSETCLR_VL>;
def SDT_RISCVMaskBinOp_VL : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
SDTCisSameAs<0, 2>,
SDTCVecEltisVT<0, i1>,
SDTCisVT<3, XLenVT>]>;
-def riscv_vmand_vl : SDNode<"RISCVISD::VMAND_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>;
-def riscv_vmor_vl : SDNode<"RISCVISD::VMOR_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>;
-def riscv_vmxor_vl : SDNode<"RISCVISD::VMXOR_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>;
+def riscv_vmand_vl : RVSDNode<"VMAND_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>;
+def riscv_vmor_vl : RVSDNode<"VMOR_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>;
+def riscv_vmxor_vl : RVSDNode<"VMXOR_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>;
def true_mask : PatLeaf<(riscv_vmset_vl (XLenVT srcvalue))>;
def riscv_vmnot_vl : PatFrag<(ops node:$rs, node:$vl),
(riscv_vmxor_vl node:$rs, true_mask, node:$vl)>;
-def riscv_vcpop_vl : SDNode<"RISCVISD::VCPOP_VL",
- SDTypeProfile<1, 3, [SDTCisVT<0, XLenVT>,
- SDTCisVec<1>, SDTCisInt<1>,
- SDTCVecEltisVT<2, i1>,
- SDTCisSameNumEltsAs<1, 2>,
- SDTCisVT<3, XLenVT>]>>;
+let HasMaskOp = true in {
+ def riscv_vcpop_vl : RVSDNode<"VCPOP_VL",
+ SDTypeProfile<1, 3, [SDTCisVT<0, XLenVT>,
+ SDTCisVec<1>, SDTCisInt<1>,
+ SDTCVecEltisVT<2, i1>,
+ SDTCisSameNumEltsAs<1, 2>,
+ SDTCisVT<3, XLenVT>]>>;
-def riscv_vfirst_vl : SDNode<"RISCVISD::VFIRST_VL",
- SDTypeProfile<1, 3, [SDTCisVT<0, XLenVT>,
- SDTCisVec<1>, SDTCisInt<1>,
- SDTCVecEltisVT<2, i1>,
- SDTCisSameNumEltsAs<1, 2>,
- SDTCisVT<3, XLenVT>]>>;
+ def riscv_vfirst_vl : RVSDNode<"VFIRST_VL",
+ SDTypeProfile<1, 3, [SDTCisVT<0, XLenVT>,
----------------
s-barannikov wrote:
Misindented by 1
https://github.com/llvm/llvm-project/pull/138381
More information about the llvm-commits
mailing list