[llvm] [RISCV] TableGen-erate RISC-V SDNodes (PR #138381)

[Sergei Barannikov via llvm-commits]

https://github.com/s-barannikov commented:

LGTM modulo indentation nits, I noted a couple that might be difficult to find.


https://github.com/llvm/llvm-project/pull/138381