[clang] [compiler-rt] [llvm] [SystemZ] Add support for half (fp16) (PR #109164)

[Jonas Paulsson via llvm-commits]

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@@ -0,0 +1,63 @@
+# RUN: llc -o - %s -mtriple=s390x-linux-gnu -mcpu=zEC12 -verify-machineinstrs \
+# RUN:   -start-before=greedy | FileCheck %s -check-prefix=CHECK
+# RUN: llc -o - %s -mtriple=s390x-linux-gnu -mcpu=z16 -verify-machineinstrs \
+# RUN:   -start-before=greedy | FileCheck %s -check-prefix=VECTOR
+
+# Test spilling / reloading fp16bit virtual registers.
+
+---
+name: fun0
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $f0h, $f2h, $f4h
+
+    ; CHECK-LABEL: fun0:
+    ; CHECK:      aghi %r15, -240
+    ; CHECK:      ste %f4, 172(%r15)          # 4-byte Spill
+    ; CHECK-NEXT: ste %f2, 164(%r15)          # 4-byte Spill
+    ; CHECK-NEXT: ste %f0, 168(%r15)          # 4-byte Spill
+    ; CHECK-NEXT: #APP
+    ; CHECK-NEXT: #NO_APP
+    ; CHECK-NEXT: le %f0, 164(%r15)           # 4-byte Reload
+    ; CHECK:      le %f0, 168(%r15)           # 4-byte Reload
+    ; CHECK:      le %f0, 172(%r15)           # 4-byte Reload
+
+    ; VECTOR-LABEL: fun0:
+    ; VECTOR:      aghi %r15, -232
+    ; VECTOR:      vsteh %v4, 166(%r15), 0     # 2-byte Folded Spill
+    ; VECTOR-NEXT: vsteh %v2, 162(%r15), 0     # 2-byte Folded Spill
+    ; VECTOR-NEXT: vsteh %v0, 164(%r15), 0     # 2-byte Folded Spill
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JonPsson1 wrote:

Fixed.

https://github.com/llvm/llvm-project/pull/109164