[llvm] [RISCV] Modify register type of extd* Xqcibm instructions (PR #134027)

[Sudharsan Veeravalli via llvm-commits]

svs-quic wrote:

> What's the reason for this restriction?

Ah should have mentioned this in the commit message. These instructions operate on a pair of registers rs1 and rs1 + 1 with no wrap around.

https://github.com/llvm/llvm-project/pull/134027