[llvm] [RISCV] Add Xqci Insn Formats (PR #132986)

LLVM Continuous Integration via llvm-commits llvm-commits at lists.llvm.org
Tue Apr 1 21:46:37 PDT 2025 

llvm-ci wrote:

LLVM Buildbot has detected a new failure on builder `ml-opt-devrel-x86-64` running on `ml-opt-devrel-x86-64-b1` while building `llvm` at step 5 "build-unified-tree".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/175/builds/16108

<details>
<summary>Here is the relevant piece of the build log for the reference</summary>

```
Step 5 (build-unified-tree) failure: build (failure)
...
12.397 [3196/64/597] Building MipsGenDisassemblerTables.inc...
12.440 [3195/64/598] Building MipsGenAsmWriter.inc...
12.478 [3194/64/599] Building MSP430GenSubtargetInfo.inc...
12.507 [3193/64/600] Building MipsGenPostLegalizeGICombiner.inc...
12.535 [3192/64/601] Building MipsGenMCPseudoLowering.inc...
12.591 [3191/64/602] Building MipsGenRegisterBank.inc...
12.612 [3190/64/603] Building MipsGenMCCodeEmitter.inc...
12.655 [3189/64/604] Building MipsGenRegisterInfo.inc...
12.867 [3188/64/605] Building MSP430GenInstrInfo.inc...
13.059 [3187/64/606] Building RISCVTargetParserDef.inc...
FAILED: include/llvm/TargetParser/RISCVTargetParserDef.inc /b/ml-opt-devrel-x86-64-b1/build/include/llvm/TargetParser/RISCVTargetParserDef.inc 
cd /b/ml-opt-devrel-x86-64-b1/build && /b/ml-opt-devrel-x86-64-b1/build/bin/llvm-min-tblgen -gen-riscv-target-def -I /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/ -I /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/include/llvm/TargetParser -I/var/lib/buildbot/.local/lib/python3.7/site-packages/tensorflow/include -I/b/ml-opt-devrel-x86-64-b1/build/include -I/b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/include /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCV.td --write-if-changed -o include/llvm/TargetParser/RISCVTargetParserDef.inc -d include/llvm/TargetParser/RISCVTargetParserDef.inc.d
Included from /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCV.td:36:
Included from /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.td:2181:
/b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td:281:41: error: Variable not defined: 'simm13_lsb0'
                                        simm13_lsb0:$imm12),
                                        ^
13.181 [3187/63/607] Building LoongArchGenInstrInfo.inc...
13.387 [3187/62/608] Building LoongArchGenDAGISel.inc...
13.443 [3187/61/609] Building AArch64GenFastISel.inc...
13.484 [3187/60/610] Building MipsGenDAGISel.inc...
13.531 [3187/59/611] Building NVPTXGenRegisterInfo.inc...
13.568 [3187/58/612] Building MipsGenFastISel.inc...
13.710 [3187/57/613] Building PPCGenCallingConv.inc...
13.829 [3187/56/614] Building ARMGenInstrInfo.inc...
14.062 [3187/55/615] Building PPCGenRegisterBank.inc...
14.115 [3187/54/616] Building PPCGenAsmWriter.inc...
14.188 [3187/53/617] Building NVPTXGenSubtargetInfo.inc...
14.230 [3187/52/618] Building PPCGenMCCodeEmitter.inc...
14.271 [3187/51/619] Building HexagonGenDAGISel.inc...
14.337 [3187/50/620] Building PPCGenAsmMatcher.inc...
14.350 [3187/49/621] Building PPCGenDisassemblerTables.inc...
14.422 [3187/48/622] Building PPCGenRegisterInfo.inc...
14.444 [3187/47/623] Building NVPTXGenAsmWriter.inc...
14.507 [3187/46/624] Building MipsGenSubtargetInfo.inc...
14.599 [3187/45/625] Building HexagonGenInstrInfo.inc...
14.658 [3187/44/626] Building SparcGenAsmMatcher.inc...
15.168 [3187/43/627] Building PPCGenSubtargetInfo.inc...
15.332 [3187/42/628] Building NVPTXGenInstrInfo.inc...
15.867 [3187/41/629] Building NVPTXGenDAGISel.inc...
16.091 [3187/40/630] Building AArch64GenGlobalISel.inc...
16.666 [3187/39/631] Building RISCVGenO0PreLegalizeGICombiner.inc...
FAILED: lib/Target/RISCV/RISCVGenO0PreLegalizeGICombiner.inc /b/ml-opt-devrel-x86-64-b1/build/lib/Target/RISCV/RISCVGenO0PreLegalizeGICombiner.inc 
cd /b/ml-opt-devrel-x86-64-b1/build && /b/ml-opt-devrel-x86-64-b1/build/bin/llvm-tblgen -gen-global-isel-combiner -combiners="RISCVO0PreLegalizerCombiner" -I /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV -I/var/lib/buildbot/.local/lib/python3.7/site-packages/tensorflow/include -I/b/ml-opt-devrel-x86-64-b1/build/include -I/b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/include -I /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/lib/Target /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCVGISel.td --write-if-changed -o lib/Target/RISCV/RISCVGenO0PreLegalizeGICombiner.inc -d lib/Target/RISCV/RISCVGenO0PreLegalizeGICombiner.inc.d
Included from /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCVGISel.td:16:
Included from /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCV.td:36:
Included from /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.td:2181:
/b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td:281:41: error: Variable not defined: 'simm13_lsb0'
                                        simm13_lsb0:$imm12),

```

</details>

https://github.com/llvm/llvm-project/pull/132986

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