[llvm] [RISCV] Add Xqci Insn Formats (PR #132986)

[LLVM Continuous Integration via llvm-commits]

llvm-ci wrote:

LLVM Buildbot has detected a new failure on builder `ml-opt-rel-x86-64` running on `ml-opt-rel-x86-64-b2` while building `llvm` at step 5 "build-unified-tree".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/185/builds/15996

<details>
<summary>Here is the relevant piece of the build log for the reference</summary>

```
Step 5 (build-unified-tree) failure: build (failure)
...
12.010 [3195/64/598] Building MipsGenMCPseudoLowering.inc...
12.071 [3194/64/599] Building MipsGenRegisterBank.inc...
12.083 [3193/64/600] Building MSP430GenSubtargetInfo.inc...
12.115 [3192/64/601] Building LoongArchGenDAGISel.inc...
12.116 [3191/64/602] Building MipsGenRegisterInfo.inc...
12.123 [3190/64/603] Building MipsGenPostLegalizeGICombiner.inc...
12.349 [3189/64/604] Building MSP430GenInstrInfo.inc...
12.566 [3188/64/605] Building LoongArchGenInstrInfo.inc...
12.587 [3187/64/606] Building MipsGenDAGISel.inc...
12.614 [3186/64/607] Building RISCVTargetParserDef.inc...
FAILED: include/llvm/TargetParser/RISCVTargetParserDef.inc /b/ml-opt-rel-x86-64-b1/build/include/llvm/TargetParser/RISCVTargetParserDef.inc 
cd /b/ml-opt-rel-x86-64-b1/build && /b/ml-opt-rel-x86-64-b1/build/bin/llvm-min-tblgen -gen-riscv-target-def -I /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/ -I /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/include/llvm/TargetParser -I/var/lib/buildbot/.local/lib/python3.7/site-packages/tensorflow/include -I/b/ml-opt-rel-x86-64-b1/build/include -I/b/ml-opt-rel-x86-64-b1/llvm-project/llvm/include /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCV.td --write-if-changed -o include/llvm/TargetParser/RISCVTargetParserDef.inc -d include/llvm/TargetParser/RISCVTargetParserDef.inc.d
Included from /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCV.td:36:
Included from /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.td:2181:
/b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td:281:41: error: Variable not defined: 'simm13_lsb0'
                                        simm13_lsb0:$imm12),
                                        ^
12.867 [3186/63/608] Building MipsGenFastISel.inc...
13.076 [3186/62/609] Building PPCGenCallingConv.inc...
13.300 [3186/61/610] Building NVPTXGenAsmWriter.inc...
13.302 [3186/60/611] Building PPCGenAsmMatcher.inc...
13.308 [3186/59/612] Building PPCGenAsmWriter.inc...
13.384 [3186/58/613] Building PPCGenRegisterBank.inc...
13.494 [3186/57/614] Building NVPTXGenRegisterInfo.inc...
13.588 [3186/56/615] Building ARMGenInstrInfo.inc...
13.630 [3186/55/616] Building AArch64GenFastISel.inc...
13.761 [3186/54/617] Building PPCGenMCCodeEmitter.inc...
13.952 [3186/53/618] Building MipsGenInstrInfo.inc...
13.954 [3186/52/619] Building MipsGenSubtargetInfo.inc...
13.985 [3186/51/620] Building PPCGenRegisterInfo.inc...
14.020 [3186/50/621] Building NVPTXGenSubtargetInfo.inc...
14.070 [3186/49/622] Building PPCGenDisassemblerTables.inc...
14.130 [3186/48/623] Building HexagonGenInstrInfo.inc...
14.246 [3186/47/624] Building HexagonGenDAGISel.inc...
14.540 [3186/46/625] Building SparcGenAsmMatcher.inc...
14.578 [3186/45/626] Building SparcGenAsmWriter.inc...
15.051 [3186/44/627] Building NVPTXGenDAGISel.inc...
15.362 [3186/43/628] Building PPCGenSubtargetInfo.inc...
15.560 [3186/42/629] Building NVPTXGenInstrInfo.inc...
15.639 [3186/41/630] Building AArch64GenGlobalISel.inc...
15.665 [3186/40/631] Building RISCVGenDisassemblerTables.inc...
FAILED: lib/Target/RISCV/RISCVGenDisassemblerTables.inc /b/ml-opt-rel-x86-64-b1/build/lib/Target/RISCV/RISCVGenDisassemblerTables.inc 
cd /b/ml-opt-rel-x86-64-b1/build && /b/ml-opt-rel-x86-64-b1/build/bin/llvm-tblgen -gen-disassembler -I /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV -I/var/lib/buildbot/.local/lib/python3.7/site-packages/tensorflow/include -I/b/ml-opt-rel-x86-64-b1/build/include -I/b/ml-opt-rel-x86-64-b1/llvm-project/llvm/include -I /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCV.td --write-if-changed -o lib/Target/RISCV/RISCVGenDisassemblerTables.inc -d lib/Target/RISCV/RISCVGenDisassemblerTables.inc.d
Included from /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCV.td:36:
Included from /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.td:2181:
/b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td:281:41: error: Variable not defined: 'simm13_lsb0'
                                        simm13_lsb0:$imm12),
                                        ^
15.791 [3186/39/632] Building RISCVGenSearchableTables.inc...

```

</details>

https://github.com/llvm/llvm-project/pull/132986