[llvm] [RISCV] Add Xqci Insn Formats (PR #132986)

LLVM Continuous Integration via llvm-commits llvm-commits at lists.llvm.org
Tue Apr 1 21:45:45 PDT 2025 

llvm-ci wrote:

LLVM Buildbot has detected a new failure on builder `ml-opt-dev-x86-64` running on `ml-opt-dev-x86-64-b1` while building `llvm` at step 5 "build-unified-tree".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/137/builds/16234

<details>
<summary>Here is the relevant piece of the build log for the reference</summary>

```
Step 5 (build-unified-tree) failure: build (failure)
...
10.632 [3202/64/558] Building MipsGenMCPseudoLowering.inc...
10.719 [3201/64/559] Building MipsGenRegisterBank.inc...
10.764 [3200/64/560] Building MipsGenDisassemblerTables.inc...
10.807 [3199/64/561] Building MSP430GenSubtargetInfo.inc...
10.862 [3198/64/562] Building MipsGenRegisterInfo.inc...
10.963 [3197/64/563] Building LoongArchGenDAGISel.inc...
11.052 [3196/64/564] Building LoongArchGenInstrInfo.inc...
11.334 [3195/64/565] Building MSP430GenInstrInfo.inc...
11.534 [3194/64/566] Building ARMGenInstrInfo.inc...
11.563 [3193/64/567] Building RISCVTargetParserDef.inc...
FAILED: include/llvm/TargetParser/RISCVTargetParserDef.inc /b/ml-opt-dev-x86-64-b1/build/include/llvm/TargetParser/RISCVTargetParserDef.inc 
cd /b/ml-opt-dev-x86-64-b1/build && /b/ml-opt-dev-x86-64-b1/build/bin/llvm-min-tblgen -gen-riscv-target-def -I /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/ -I /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/include/llvm/TargetParser -I/b/ml-opt-dev-x86-64-b1/build/include -I/b/ml-opt-dev-x86-64-b1/llvm-project/llvm/include /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCV.td --write-if-changed -o include/llvm/TargetParser/RISCVTargetParserDef.inc -d include/llvm/TargetParser/RISCVTargetParserDef.inc.d
Included from /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCV.td:36:
Included from /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.td:2181:
/b/ml-opt-dev-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td:281:41: error: Variable not defined: 'simm13_lsb0'
                                        simm13_lsb0:$imm12),
                                        ^
11.627 [3193/63/568] Building CXX object lib/Target/ARM/Utils/CMakeFiles/LLVMARMUtils.dir/ARMBaseInfo.cpp.o
11.769 [3193/62/569] Building MipsGenFastISel.inc...
11.798 [3193/61/570] Building MipsGenDAGISel.inc...
11.830 [3193/60/571] Building PPCGenCallingConv.inc...
11.976 [3193/59/572] Building MipsGenSubtargetInfo.inc...
12.020 [3193/58/573] Building HexagonGenInstrInfo.inc...
12.122 [3193/57/574] Building PPCGenExegesis.inc...
12.208 [3193/56/575] Building NVPTXGenRegisterInfo.inc...
12.231 [3193/55/576] Building PPCGenAsmWriter.inc...
12.248 [3193/54/577] Building MipsGenGlobalISel.inc...
12.255 [3193/53/578] Building AArch64GenFastISel.inc...
12.299 [3193/52/579] Building PPCGenDisassemblerTables.inc...
12.314 [3193/51/580] Building PPCGenAsmMatcher.inc...
12.436 [3193/50/581] Building NVPTXGenAsmWriter.inc...
12.575 [3193/49/582] Building HexagonGenDAGISel.inc...
12.764 [3193/48/583] Building NVPTXGenSubtargetInfo.inc...
13.052 [3193/47/584] Building SparcGenAsmMatcher.inc...
13.112 [3193/46/585] Building SparcGenAsmWriter.inc...
13.430 [3193/45/586] Building PPCGenSubtargetInfo.inc...
13.501 [3193/44/587] Building PPCGenFastISel.inc...
13.995 [3193/43/588] Building NVPTXGenDAGISel.inc...
14.233 [3193/42/589] Building NVPTXGenInstrInfo.inc...
14.266 [3193/41/590] Building RISCVGenAsmMatcher.inc...
FAILED: lib/Target/RISCV/RISCVGenAsmMatcher.inc /b/ml-opt-dev-x86-64-b1/build/lib/Target/RISCV/RISCVGenAsmMatcher.inc 
cd /b/ml-opt-dev-x86-64-b1/build && /b/ml-opt-dev-x86-64-b1/build/bin/llvm-tblgen -gen-asm-matcher -I /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/lib/Target/RISCV -I/b/ml-opt-dev-x86-64-b1/build/include -I/b/ml-opt-dev-x86-64-b1/llvm-project/llvm/include -I /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/lib/Target /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCV.td --write-if-changed -o lib/Target/RISCV/RISCVGenAsmMatcher.inc -d lib/Target/RISCV/RISCVGenAsmMatcher.inc.d
Included from /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCV.td:36:
Included from /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.td:2181:
/b/ml-opt-dev-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td:281:41: error: Variable not defined: 'simm13_lsb0'
                                        simm13_lsb0:$imm12),
                                        ^
14.639 [3193/40/591] Building AArch64GenGlobalISel.inc...
14.835 [3193/39/592] Building RISCVGenAsmWriter.inc...

```

</details>

https://github.com/llvm/llvm-project/pull/132986

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