[llvm] [Clang][AArch64] Model ZT0 table using inaccessible memory (PR #133727)

[Paul Walker via llvm-commits]

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@@ -3031,11 +3031,11 @@ let TargetPrefix = "aarch64" in {
 
   def int_aarch64_sme_write_lane_zt
        :  DefaultAttrsIntrinsic<[], [llvm_i32_ty, llvm_anyvector_ty, llvm_i32_ty],
-            [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>, IntrNoMem, IntrHasSideEffects]>;
+            [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>, IntrInaccessibleMemOnly, IntrWriteMem]>;
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paulwalker-arm wrote:

This is a partial write and thus should also include IntrReadMem for the "passthrough" lanes?

https://github.com/llvm/llvm-project/pull/133727