[llvm] [Clang][AArch64] Model ZT0 table using inaccessible memory (PR #133727)

[Paul Walker via llvm-commits]

================
@@ -3808,50 +3808,50 @@ let TargetPrefix = "aarch64" in {
   def int_aarch64_sve_sel_x4  : SVE2_VG4_Sel_Intrinsic;
 
   class SME_LDR_STR_ZT_Intrinsic
-    : DefaultAttrsIntrinsic<[], [llvm_i32_ty, llvm_ptr_ty]>;
+    : DefaultAttrsIntrinsic<[], [llvm_i32_ty, llvm_ptr_ty], [IntrInaccessibleMemOrArgMemOnly]>;
----------------
paulwalker-arm wrote:

With the new modelling has the common base class lost its value? given we'll want to mark one as write only and the other as read only.

https://github.com/llvm/llvm-project/pull/133727