[llvm] [AArch64][SVE] Lower unpredicated loads/stores as fixed LDR/STR with -msve-vector-bits=128. (PR #127500)

[Paul Walker via llvm-commits]

paulwalker-arm wrote:

> I believe I've addressed most of your feedback. I also have a tentative patch implementing the SVE LDR/STR pairing you initially suggested. Would you prefer I open a separate PR for this, or should I include it in this patch so we can decide on the approach to go for?

Please use a separate PR for the SVE LDR/STR pairing approach. Doing this means this PR can remain in reserve if for some reason we decide to reverse the current direction of travel.

https://github.com/llvm/llvm-project/pull/127500