[llvm] [MIPS] Add Scheduling model for MIPS i6400 and i6500 CPUs (PR #132704)

[Min-Yih Hsu via llvm-commits]

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+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=mips64el -mcpu=i6400 -timeline -iterations=1 < %s | FileCheck %s
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mshockwave wrote:

> I wanted to test dispatch and execute timeline. do you suggest to remove --timeline from this test?

The scheduling model tests are supposed to check if the latency and occupancy (i.e. AcquireAtCycle / ReleaseAtCycle) show up correctly as expected. The basic MCA views already present those two metrics without `-timeline`. Testing with an additional `-timeline` wouldn't add much because it's nearly impossible for a scheduling model to "break" MCA's logics on how to calculate dispatch & execution cycles. That's why I would suggest removing `-timeline`

https://github.com/llvm/llvm-project/pull/132704