[llvm] [MIPS] Add Scheduling model for MIPS i6400 and i6500 CPUs (PR #132704)

[Min-Yih Hsu via llvm-commits]

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@@ -983,7 +983,10 @@ let AdditionalPredicates = [NotInMicroMips] in {
   def SEL_S : R6MMR6Rel, SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6, HARDFLOAT;
   def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
   def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;
-  def SIGRIE : SIGRIE_ENC, SIGRIE_DESC, ISA_MIPS32R6;
+  
+  let hasNoSchedulingInfo = true in {
+    def SIGRIE : SIGRIE_ENC, SIGRIE_DESC, ISA_MIPS32R6;
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mshockwave wrote:

if these instructions never have scheduling information. Why haven't other scheduling models complained about it (during TableGen generation time)?
Is it possible to set your new I6400 model with `CompleteModel = 0` instead of changing the instruction definition here?

https://github.com/llvm/llvm-project/pull/132704