[llvm] [RISCV] Move RISCVVMV0Elimination past pre-ra scheduling (PR #132057)

[Luke Lau via llvm-commits]

lukel97 wrote:

Yes I was looking a bit deeper into this too, I found this explanation which might be more useful https://lists.llvm.org/pipermail/llvm-dev/2016-May/100019.html

If I'm understanding this correctly the limit is the maximum number of register units that might interfere with the virtual register set? So if something is assigned to v0m8 it would add 8 to VMV0's pressure set?

https://github.com/llvm/llvm-project/pull/132057