[llvm] [RISCV] Move RISCVVMV0Elimination past pre-ra scheduling (PR #132057)

[Pengcheng Wang via llvm-commits]

wangpc-pp wrote:

Some updates: we can't simply set the limit of VMV0 to smaller values (2 for example).
Here is the log when building reg pressure sets:
```
UnitSet 31 VMV0: V0
UnitSet 33 VRM2_with_sub_vrm1_0_in_VMV0: V0 V1
UnitSet 34 VRN3M1_with_sub_vrm1_0_in_VMV0: V0 V1 V2
UnitSet 36 VRM4_with_sub_vrm1_0_in_VMV0: V0 V1 V2 V3
UnitSet 37 VRN5M1_with_sub_vrm1_0_in_VMV0: V0 V1 V2 V3 V4
UnitSet 38 VRN3M2_with_sub_vrm1_0_in_VMV0: V0 V1 V2 V3 V4 V5
UnitSet 39 VRN7M1_with_sub_vrm1_0_in_VMV0: V0 V1 V2 V3 V4 V5 V6
UnitSet 41 VRM8_with_sub_vrm1_0_in_VMV0: V0 V1 V2 V3 V4 V5 V6 V7
UnitSet 31 subsumed by 33
UnitSet 33 subsumed by 34
UnitSet 34 subsumed by 36
UnitSet 36 subsumed by 37
UnitSet 37 subsumed by 38
UnitSet 38 subsumed by 39
UnitSet 39 subsumed by 41
```
The reason why it is 8 is because we have some synthesized register classes and VMV0 is subsumed by these classes. This causes the unreasonable higher limit of VMV0. There must be something wrong somewhere but I'm still investigating (the way we model register class is complicated and I don't know if there is a person who are still working on that since it hasn't been changed for decades 😢).

https://github.com/llvm/llvm-project/pull/132057