[llvm] [RISCV] Move RISCVVMV0Elimination past pre-ra scheduling (PR #132057)

[Pengcheng Wang via llvm-commits]

wangpc-pp wrote:

> Yes I was looking a bit deeper into this too, I found this explanation which might be more useful https://lists.llvm.org/pipermail/llvm-dev/2016-May/100019.html
> 
> If I'm understanding this correctly the limit is the maximum number of register units that might interfere with the virtual register set? So if something is assigned to v0m8 it would add 8 to VMV0's pressure set?

Yes, we will add the return value of `getRegClassWeight` to the VMV0 pressure set.
Here is the problem:
1. Register classes `VMV0` and `VRM8_with_sub_vrm1_0_in_VMV0` share the same pressure set (which is also named `VMV0`).
2. The `RegClassWeight` is 1 for register class `VMV0` and 8 for register class `VRM8_with_sub_vrm1_0_in_VMV0`.
3. The limit of the VMV0 pressure set is 8 here.
4. So IIUC, there is mismatch that the scheduler think it can allocate 8 registers of register class `VMV0` before it reaches the limit 8. This may cause higher register pressure than the actual.

https://github.com/llvm/llvm-project/pull/132057