[llvm] [RISCV] Move RISCVVMV0Elimination past pre-ra scheduling (PR #132057)

[Luke Lau via llvm-commits]

lukel97 wrote:

Looks like there's a 10% regression in x264 with this patch: https://lnt.lukelau.me/db_default/v4/nts/348?show_delta=yes&show_previous=yes&show_stddev=yes&show_mad=yes&show_all=yes&show_all_samples=yes&num_comparison_runs=0&test_filter=&test_min_value_filter=&aggregation_fn=min&MW_confidence_lv=0.05&compare_to=352&submit=Update

>From a quick glance there does seem to be a lot more spilling in one of the kernels, so I think you may be right about the register pressure calculation being off! Will investigate further

https://github.com/llvm/llvm-project/pull/132057