[llvm] [RISCV] Move RISCVVMV0Elimination past pre-ra scheduling (PR #132057)

[Luke Lau via llvm-commits]

lukel97 wrote:

@wangpc-pp I've also been meaning to look at `getRegPressureSetLimit` I haven't forgotten! I've just also been waiting on a run on the BPI-F3 to finish, my build machine unfortunately ran out of disk space over the weekend so I had to start it again this morning 🙃 Hopefully I'll have results by tomorrow

https://github.com/llvm/llvm-project/pull/132057