[llvm] [RISCV] Move RISCVVMV0Elimination past pre-ra scheduling (PR #132057)

[Philip Reames via llvm-commits]

preames wrote:

> Apparently, the limit 8 of `VMV0` is not right since there is only one register in it. But if we override `getRegPressureSetLimit` in `RISCVInstrInfo` and returns 1 or 2 for `VMV0`, we may meet similar problem in RA (`out of registers`). But I encourage you to try this way. :-)

Could I ask you to file an issue with your failure reproducers?  I just tried the limit of 2 locally, and didn't see any obvious problems in make check-llvm.  I've got a little bit of weirdness in test changes, but no failures.

https://github.com/llvm/llvm-project/pull/132057