[llvm] [AMDGPU][True16][CodeGen] update waitcnt for true16 (PR #128927)

Brox Chen via llvm-commits llvm-commits at lists.llvm.org
Thu Mar 6 12:33:32 PST 2025


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@@ -757,30 +769,31 @@ RegInterval WaitcntBrackets::getRegInterval(const MachineInstr *MI,
 
   RegInterval Result;
 
-  unsigned Reg = TRI->getEncodingValue(AMDGPU::getMCReg(Op.getReg(), *ST)) &
-                 AMDGPU::HWEncoding::REG_IDX_MASK;
+  unsigned Reg = getRegPoint(*ST, Op.getReg(), *TRI);
+  const TargetRegisterClass *RC = TRI->getPhysRegBaseClass(Op.getReg());
+  unsigned Size = TRI->getRegSizeInBits(*RC);
 
+  // VGPRs are tracked every 16 bits, SGPRs by 32 bits
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broxigarchen wrote:

Updated the comment.

It seems https://github.com/llvm/llvm-project/issues/105814 is about optimizing spgr intervals. I think that can be done in a seperate patch

https://github.com/llvm/llvm-project/pull/128927


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