[llvm] [AMDGPU] Filter candidates of LiveRegOptimizer for profitable cases (PR #124624)

[Jeffrey Byrnes via llvm-commits]

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@@ -125,6 +127,131 @@ class LiveRegOptimizer {
     return LK.first != TargetLoweringBase::TypeLegal;
   }
 
+  /// Check if intrinsic natively operates on 8-bit or 16-bit
+  bool isNativeIntrinsic(Intrinsic::ID ID) {
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jrbyrnes wrote:

> Not clear to me what this means

"intrinsic / instruction can natively handle illegal vector types" = The target intrinsic has either bytewise logic on the 32 bit regs (like mfma) or type doesn't matter (i.e. store). 

For a standard instruction (e.g. v4i8 add), the compiler will need to insert scalarization code.

We should probably just use isTargetIntrinsic and narrow it as needed.

https://github.com/llvm/llvm-project/pull/124624