[llvm] [RISCV] Check feature bits in getBrCond (PR #129859)

[Pengcheng Wang via llvm-commits]

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@@ -45,7 +45,8 @@ enum CondCode {
 };
 
 CondCode getOppositeBranchCondition(CondCode);
-unsigned getBrCond(CondCode CC, bool Imm = false);
+unsigned getBrCond(CondCode CC, const FeatureBitset &FeatureBits,
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wangpc-pp wrote:

Pass RISCVSubtarget?

https://github.com/llvm/llvm-project/pull/129859