[llvm] 4670f0d - MachineVerifier: Print name of failing subregister index (#129491)
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Mon Mar 3 20:25:37 PST 2025
Author: Matt Arsenault
Date: 2025-03-04T11:25:34+07:00
New Revision: 4670f0d8275a7eacfba46a17d88d3e2d947f5a61
URL: https://github.com/llvm/llvm-project/commit/4670f0d8275a7eacfba46a17d88d3e2d947f5a61
DIFF: https://github.com/llvm/llvm-project/commit/4670f0d8275a7eacfba46a17d88d3e2d947f5a61.diff
LOG: MachineVerifier: Print name of failing subregister index (#129491)
I'm not sure of a good example to test the "does not fully support"
case.
Added:
Modified:
llvm/lib/CodeGen/MachineVerifier.cpp
llvm/test/MachineVerifier/AMDGPU/unsupported-subreg-index-aligned-vgpr-check.mir
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 4ab6fc2ddc28c..87d3033038414 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -2749,13 +2749,15 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
if (!SRC) {
report("Invalid subregister index for virtual register", MO, MONum);
OS << "Register class " << TRI->getRegClassName(RC)
- << " does not support subreg index " << SubIdx << '\n';
+ << " does not support subreg index "
+ << TRI->getSubRegIndexName(SubIdx) << '\n';
return;
}
if (RC != SRC) {
report("Invalid register class for subregister index", MO, MONum);
OS << "Register class " << TRI->getRegClassName(RC)
- << " does not fully support subreg index " << SubIdx << '\n';
+ << " does not fully support subreg index "
+ << TRI->getSubRegIndexName(SubIdx) << '\n';
return;
}
}
diff --git a/llvm/test/MachineVerifier/AMDGPU/unsupported-subreg-index-aligned-vgpr-check.mir b/llvm/test/MachineVerifier/AMDGPU/unsupported-subreg-index-aligned-vgpr-check.mir
index 651a9d71ae320..be1311cb6b217 100644
--- a/llvm/test/MachineVerifier/AMDGPU/unsupported-subreg-index-aligned-vgpr-check.mir
+++ b/llvm/test/MachineVerifier/AMDGPU/unsupported-subreg-index-aligned-vgpr-check.mir
@@ -19,7 +19,7 @@ body: |
; CHECK-NEXT: - basic block: %bb.0
; CHECK-NEXT: - instruction: GLOBAL_STORE_DWORDX4_SADDR %0:vgpr_32, %1.sub16_sub17_sub18_sub19:vreg_512_align2, undef $sgpr8_sgpr9, 80, 0, implicit $exec :: (store (s128), addrspace 1)
; CHECK-NEXT: - operand 1: %1.sub16_sub17_sub18_sub19:vreg_512_align2
- ; CHECK-NEXT: Register class VReg_512_Align2 does not support subreg index 166
+ ; CHECK-NEXT: Register class VReg_512_Align2 does not support subreg index sub16_sub17_sub18_sub19
; CHECK: *** Bad machine code: Subtarget requires even aligned vector registers ***
; CHECK-NEXT: - function: uses_invalid_subregister_for_regclass
@@ -33,7 +33,7 @@ body: |
; CHECK-NEXT: - basic block: %bb.0
; CHECK-NEXT: - instruction: GLOBAL_STORE_DWORDX4_SADDR %0:vgpr_32, %2.sub16_sub17_sub18_sub19:vreg_512, undef $sgpr8_sgpr9, 80, 0, implicit $exec :: (store (s128), addrspace 1)
; CHECK-NEXT: - operand 1: %2.sub16_sub17_sub18_sub19:vreg_512
- ; CHECK-NEXT: Register class VReg_512 does not support subreg index 166
+ ; CHECK-NEXT: Register class VReg_512 does not support subreg index sub16_sub17_sub18_sub19
S_NOP 0, implicit-def %2:vreg_512
GLOBAL_STORE_DWORDX4_SADDR %0, %2.sub16_sub17_sub18_sub19, undef $sgpr8_sgpr9, 80, 0, implicit $exec :: (store (s128), addrspace 1)
S_ENDPGM 0
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