[llvm] [SelectionDAG] Add PARTIAL_REDUCE_U/SMLA ISD Nodes (PR #125207)

[Paul Walker via llvm-commits]

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@@ -1451,6 +1451,19 @@ enum NodeType {
   VECREDUCE_UMAX,
   VECREDUCE_UMIN,
 
+  // PARTIAL_REDUCE_[U|S]MLA(Accumulator, Input1, Input2)
+  // The partial reduction nodes sign or zero extend Input1 and Input2 to
+  // the element type of Accumulator before multiplying their results.
+  // The multiplied result is then reduced using addition to the result
+  // type of Accumulator. The result is added to Accumulator and returned.
+  // Input1 and Input2 must be the same type. Accumulator and the output must be
+  // the same type.
+  // The number of elements in Input1 and Input2 must be a positive integer
+  // multiple of the number of elements in the Accumulator / output type.
+  // All operands, as well as the output, must have the same element type.
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paulwalker-arm wrote:

This final line is bogus? because the whole intent of the operation is to allow for multiply operands that have a different element type to the accumulator. Being more specific, the operation requires the multiply operands to be the same or smaller than the accumulator type.

https://github.com/llvm/llvm-project/pull/125207