[llvm] [SelectionDAG] Add PARTIAL_REDUCE_U/SMLA ISD Nodes (PR #125207)

[Paul Walker via llvm-commits]

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@@ -1451,6 +1451,19 @@ enum NodeType {
   VECREDUCE_UMAX,
   VECREDUCE_UMIN,
 
+  // PARTIAL_REDUCE_[U|S]MLA(Accumulator, Input1, Input2)
+  // The partial reduction nodes sign or zero extend Input1 and Input2 to
+  // the element type of Accumulator before multiplying their results.
+  // The multiplied result is then reduced using addition to the result
+  // type of Accumulator. The result is added to Accumulator and returned.
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paulwalker-arm wrote:

This is too strict and should be relaxed to match the behaviour of the partial reduction intrinsic. Specially, the multiplied result is concatenated to the accumulator and this combined vector is reduced using addition down to the result type.

https://github.com/llvm/llvm-project/pull/125207