[llvm] [SelectionDAG] Add PARTIAL_REDUCE_U/SMLA ISD Nodes (PR #125207)

[Paul Walker via llvm-commits]

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@@ -2881,6 +2890,13 @@ SDValue DAGTypeLegalizer::PromoteIntOp_VECTOR_FIND_LAST_ACTIVE(SDNode *N,
   return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
 }
 
+SDValue DAGTypeLegalizer::PromoteIntOp_PARTIAL_REDUCE_MLA(SDNode *N,
+                                                          unsigned OpNo) {
+  SmallVector<SDValue, 1> NewOps(N->ops());
+  NewOps[OpNo] = GetPromotedInteger(N->getOperand(OpNo));
+  return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
+}
+
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paulwalker-arm wrote:

Does this potentially lead to the ISD node being in an inconsistent state? because `PARTIAL_REDUCE_*MLA` requires its multiply operands to be the same type.

I would expect `OpNo` to be either 1 or 2 because by this point we can be sure the result is type legal and hence the first operand must also be type legal. When that happens I'd expect both operands to be promoted at the same time so the underling `PARTIAL_REDUCE_*MLA` operation remains consistent.

https://github.com/llvm/llvm-project/pull/125207