[llvm] clastb representation in existing IR, and AArch64 codegen (PR #112738)

[Benjamin Maxwell via llvm-commits]

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@@ -840,6 +840,9 @@ def vector_insert_subvec : SDNode<"ISD::INSERT_SUBVECTOR",
 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;
 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>;
 
+def find_last_active
+    : SDNode<"ISD::VECTOR_FIND_LAST_ACTIVE", SDTypeProfile<1, 1, []>, []>;
+
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MacDue wrote:

Is it worth adding any constrains for `find_last_active`?

https://github.com/llvm/llvm-project/pull/112738