[llvm] [AArch64][SME] Make getRegAllocationHints stricter for multi-vector loads (PR #123081)

[Sander de Smalen via llvm-commits]

https://github.com/sdesmalen-arm approved this pull request.

LGTM with nit addressed.

Would it make sense to update the title/commit message to reflect that you've also made it less strict? i.e. extracting one column from 4 x 2-vector loads can be used with an instruction that requires sequential regs now.

https://github.com/llvm/llvm-project/pull/123081