[llvm] [AArch64][SME] Make getRegAllocationHints stricter for multi-vector loads (PR #123081)

[Sander de Smalen via llvm-commits]

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@@ -1099,6 +1100,11 @@ bool AArch64RegisterInfo::getRegAllocationHints(
     const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
   const MachineRegisterInfo &MRI = MF.getRegInfo();
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sdesmalen-arm wrote:

nit: this can be moved down (after the if(..) condition)

https://github.com/llvm/llvm-project/pull/123081