[llvm] [RISCV] Generate MIPS load/store pair instructions (PR #124717)

[Craig Topper via llvm-commits]

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@@ -0,0 +1,364 @@
+//===----- RISCVLoadStoreOptimizer.cpp ------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Bundle loads and stores that operate on consecutive memory locations to take
+// the advantage of hardware load/store bonding.
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topperc wrote:

"the" is unnecesary i this sentence.

https://github.com/llvm/llvm-project/pull/124717