[llvm] [CodeGen] Add MachineRegisterClassInfo analysis pass (PR #120690)

[Pengcheng Wang via llvm-commits]

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@@ -345,9 +347,11 @@
 ; GCN-O1-NEXT:        Slot index numbering
 ; GCN-O1-NEXT:        Live Interval Analysis
 ; GCN-O1-NEXT:        Machine Natural Loop Construction
+; GCN-O1-NEXT:        Machine Register Class Info Analysis
 ; GCN-O1-NEXT:        Register Coalescer
 ; GCN-O1-NEXT:        Rename Disconnected Subregister Components
 ; GCN-O1-NEXT:        Rewrite Partial Register Uses
+; GCN-O1-NEXT:        Machine Register Class Info Analysis
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wangpc-pp wrote:

That will be a lot of work? I haven't make regalloc use this pass yet so there is no worry about this currently.

https://github.com/llvm/llvm-project/pull/120690