[llvm] [TableGen][GISel] Create untyped registers during instruction selection (PR #121270)

[Matt Arsenault via llvm-commits]

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@@ -1485,15 +1485,28 @@ bool GIMatchTableExecutor::executeMatchTable(
       propagateFlags();
       return true;
     }
-    case GIR_MakeTempReg: {
+    case GIR_MakeGenericTempReg: {
       uint64_t TempRegID = readULEB();
       int TypeID = readS8();
 
       State.TempRegisters[TempRegID] =
           MRI.createGenericVirtualRegister(getTypeFromIdx(TypeID));
-      DEBUG_WITH_TYPE(TgtExecutor::getName(),
-                      dbgs() << CurrentIdx << ": TempRegs[" << TempRegID
-                             << "] = GIR_MakeTempReg(" << TypeID << ")\n");
+      DEBUG_WITH_TYPE(TgtExecutor::getName(), {
+        dbgs() << CurrentIdx << ": TempRegs[" << TempRegID
+               << "] = GIR_MakeGenericTempReg(" << TypeID << ")\n";
+      });
+      break;
+    }
+    case GIR_MakeVirtualTempReg: {
+      uint64_t TempRegID = readULEB();
+
+      Register Reg = MRI.createIncompleteVirtualRegister();
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arsenm wrote:

> Why do you think fixing the register class by emitting a COPY is better left to instruction selector?

I don't, ideally tablegen would fully understand the set of instructions that need to be emitted here and explicitly handle it. But as far as a hack to make progress goes, I think that's better than using incomplete registers if it's hard to get tablegen into a state where that is possible 

https://github.com/llvm/llvm-project/pull/121270